In a system with multiple coupled digital phase-locked loops (DPLLs), one or more receiving DPLLs can adjust a respective frequency offset from a loop filter within the receiving DPLLs using one or more frequency offsets received from multiple sourcing DPLLs. For example, one sourcing DPLL could be locked to a system Oven Controlled Crystal Oscillator (OCXO) or Temperature Controlled Crystal Oscillator (TCXO) while another sourcing DPLL could be locked to a network clock. The receiving DPLL could be locked to a packet stream. The coupling from the two sourcing DPLLs would enhance the stability of the receiving DPLL. When more than two DPLLs are coupled, the complexity of the wiring connections between the DPLLs grows rapidly.
It would be desirable to implement a time slotted bus system for multiple coupled DPLLs.